The technology disclosed herein relates to non-volatile semiconductor memory devices including a gate insulating film having a trap level which can accumulate electric charge, and more particularly, to non-volatile semiconductor memory devices including an ultra-violet (UV) light shielding film.
There are known non-volatile semiconductor devices which store information using an insulating film which can trap electric charge. An example of the non-volatile semiconductor devices includes a gate insulating film including a silicon nitride film having a trap level, a source region, and a drain region. In this non-volatile semiconductor device, hot electrons generated in the drain edge are injected into an oxide nitride oxide (ONO) film in the vicinity of the drain so that electrons are accumulated in the silicon nitride film, whereby information is stored.
In a method for fabricating the non-volatile semiconductor memory device, after a memory cell array is formed, an interlayer insulating film is formed, and metal wirings which serve as electrodes for operating memory cells are formed. In this case, a plasma process of generating UV is used after formation of the memory cell array.
For example, plasma etching is used to create contact holes, and UV light is generated in the plasma etching process. If the generated UV light enters the semiconductor substrate, electrons may be excited and then trapped in the ONO film to increase the threshold (Vt) of the memory cell.
As described above, data is written to the MONOS memory cell by injecting electrons into the ONO film. In this case, if excited electrons generated by UV light are injected into the ONO film, the overall amount of electrons injected thereinto becomes excessive. Therefore, the threshold Vt becomes higher than a value which is previously set to a level required for write operation. In particular, data stored in the memory cell is erased by injecting holes generated by a band-to-band tunneling (BTBT) current into the ONO film to neutralize electrons trapped in the ONO film. Therefore, if Vt is increased, excited electrons trapped in the ONO film cannot be completely neutralized. As a result, the memory cell cannot be lowered to Vt which is previously set to an erase level, which is a problem.
If, for the reason described above, excited electrons generated by UV light are trapped in the ONO film, it is significantly difficult to regulate Vt for write operation and erase operation of the memory cell, leading to a reduction in reliability of the memory cell.
In order to overcome this problem, it is known that a UV light shielding film is provided to cover at least the memory cell region so that UV light which is generated in a wiring fabricating step and then enters the memory cell region is reduced or prevented.
FIG. 23 is a plan view showing a layout of a conventional non-volatile semiconductor memory device. FIG. 24 is a cross-sectional view of the non-volatile semiconductor memory device, taken along line XXIV-XXIV of FIG. 23.
As shown in FIGS. 23 and 24, the conventional non-volatile semiconductor memory device includes a memory cell array (memory cell region) in which a plurality of bit lines 101 and a plurality of word lines 102 orthogonally intersecting the bit lines 101 are provided. The bit lines 101 are formed by introducing an n-type impurity into an upper portion of a p-type well region 143 on a semiconductor substrate 141. The bit lines 101 and the word lines 102 are electrically separated from each other by a bit line oxide film 110.
An ONO film (not shown) is provided in a region between a well region 143 and the word lines 102, which is located between adjacent bit lines 101 as viewed from the top. Therefore, each memory cell has a constitution similar to that of a MOS transistor in which the gate insulating film is replaced with the ONO film. In this non-volatile semiconductor memory device, data is written or erased by selecting an appropriate bit line 101 and word line 102 from the plurality of bit lines 101 and the plurality of word lines 102.
The word lines 102 are covered with an insulating film 150. A first interlayer insulating film 120 is provided on the insulating film 150 and the well region 143. A UV light shielding film 121 is provided on the first interlayer insulating film 120. A second interlayer insulating film 122 is provided on the UV light shielding film 121 and the first interlayer insulating film 120.
As shown in FIG. 23, the UV light shielding film 121 covers an entirety of the memory cell region. As a result, it is difficult for UV light generated in the process of forming wirings 200 to enter the semiconductor substrate, the ONO film and the like in the memory cell region. Note that, in FIG. 23, lines inside the UV light shielding film 121 indicate active regions 170 which are portions of the semiconductor substrate. Other active regions 170 are provided in regions surrounding bit line contacts 130 as viewed from the top. The active regions are electrically separated from each other by isolation regions.